1. Field of the Invention
The present invention relates generally to a DRAM direct sensing scheme, and more particularly pertains to a DRAM direct sensing scheme which relies upon the pFET threshold voltage of a pFET device to detect a signal development level with a significant reduction in the number of devices in the primary sense amplifier.
In the design of DRAMs, the direct sensing scheme is emerging and becoming more popular because future DRAMs need to use a lower bitline voltage. This restriction is applied from both scaling and performance points of view. From the scaling point of view, the device sizes need to be reduced to obtain a higher density of the memory. This requires reduced operation voltages to meet the reliability specifications and basic device performance requirements like the device threshold voltage Vt roll-off. Performance requirements such as speed require a lower bit-line high voltage Vblh to obtain more overdrive of array devices with a limited word line voltage Vpp. The word line voltage Vpp is limited by the gate oxide thickness, which is reduced as the device size is reduced. This is especially true for the write back operation.
If Vblh is reduced, however, the conventional 1/2 Vblh sensing scheme adopted in most DRAMs on the market is not practical to implement due to its low signal development. This encourages the direct sensing scheme.
Simultaneously, lowering the operating voltages, especially lowering Vpp, makes it more difficult to writeback xe2x80x9chighxe2x80x9d data into the cell. This is based upon the fact that the back bias of the array device increases as xe2x80x9chighxe2x80x9d data is written into the cell, which increases Vt and reduces the overdrive of the array device. This adversely impacts the writeback time of the xe2x80x9chighxe2x80x9d cell, which limits high speed applications.
One way to solve the above problem is to only sense xe2x80x9clowxe2x80x9d with a direct sensing scheme and a VDD precharge level. One problem with this scheme, however, is the very small signal difference between xe2x80x9clowxe2x80x9d and xe2x80x9chighxe2x80x9d cells, because the cell voltage of the xe2x80x9chighxe2x80x9d cell is not well defined. Therefore, one approach is to amplify the developed signal.
Because this is a DRAM, it is necessary to writeback the data after reading it. The read operation in a DRAM is inherently destructive of the data because once the transistor for a memory cell is switched on, the charge on the memory cell capacitator dissipates onto the bitline and eliminates its once readable logic level. Therefore, conventional DRAMs employ a writeback cycle as part of the read operation. With a conventional sense amplifier circuit, there is a delay between the time the accessed sense amplifier detects data from the memory cell and the time the data can be fully written back to the data cell, because of the extra loading on the bit line of the data line (DQ) which carries the data out of the primary sense amplifier. By employing a sense amplifier which terminates the bit line into the gate of the transistor, the bit line is decoupled from the loading of the DQ line which both reduces the time sense data, and also improves the ability to sense the data correctly.
2. Discussion of the Prior Art
For applications which require a fast random access time, the traditional CMOS cross-coupled sense amp has limitations in both sensing time and writeback. The writeback limitation can be avoided by performing a technique such as a destructive read operation (Disclosure: Toshi Kirihata et al). The sensing time limits the memory cycle time because the bitline signal must be amplified and transferred to a dataline. Sensing a small bitline signal and transferring it to a digital data line with traditional techniques requires more than 5 ns. Hence the need for higher speed direct sense techniques.
1) Conventional cross-coupled sense amps without reference cells require a VDD/2 bitline voltage precharge. When the sense amps are set, positive moving bitlines couple unselected wordlines upward, which increases cell leakage.
2) A conventional direct sensing scheme with a current mirror sense amplifier uses a bitline pair and a data line pair per bit. A current mirror sense amplifier requires a large design space, resulting in poor density and an expensive solution.
3) Some DRAM macros require sensing and reading out of every bitline signal, rather than decoding a portion of the senseamps and reading out a subset. This requires a read/write head which can couple the sense amp data to external datalines without creating a read disturb. A read disturb occurs when a precharged dataline is connected to a sense amp. This effect is reduced if a pair of datalines are connected to both true and complement sense amp nodes. In dense DRAM macros where every cell along a wordline must be outputted, there is a large area penalty to operate with differential datalines and their associated circuitry. In some cases, it is impossible to arrange a differential data line pair for each bitline pair because of design rule constraints, which makes it difficult or impossible to use a conventional direct sensing scheme.
4) As technology advances to smaller lithographies, voltages must be scaled to lower levels to reduce oxide stress. It is known that the device threshold voltage Vt does not scale efficiently with power supply, and so overdrive is lost on FETs. VDD/2 sensing schemes must operate with very low overdrive at low power supplies, and hence suffer a large degradation in sensing speed as the device Vt increases at low temperatures.
5) Testing of on-chip DRAM macros is difficult because of pattern sensitivities. One advantage of the sensing scheme of the present invention is that only every other bitline is active, so that alternating bitlines can be held at AC ground to eliminate line to line coupling effects. The increased bitline signal also increases sensing margin.
6) It is preferable to maintain the same polarity (even number of signal inversions) between the bitline BL signal and the dataline (DQ) signal. If this condition is met, the primary sense amplifier can be employed to write-back data into the storage capacitor.
7) It is preferable to minimize logical xe2x80x9cglitchesxe2x80x9d on the datalines (DQs) so that dynamic logic can be used to control the data buses. Here, a xe2x80x9cglitchxe2x80x9d is defined as a signal waveform that will cause a logical error if it is an input to a dynamic logic gate.
Atsumi et al (ISSCC 2000, p276) discusses a direct sensing scheme for EEPROM with a sense amplifier using an NFET. This requires a reference bitline, and no feedback loop exists to writeback data to the bitline (because this is an EEPROM).
Suh et al (J. Solid State Circuits, 31, 1025 (1996)) discusses a direct sensing scheme for a DRAM which needs a reference voltage to power the rewrite amplifier and uses an NFET for the sensing.
FIG. 1 illustrates a typical prior art direct sensing circuit using both a direct sensing block and also a cross-coupled sensing block. The direct sensing circuit block consists of a read portion 104 and a write portion 105. The read portion is triggered by a read control RE. The write portion is triggered by a write control WE. A pair of switches N10 and N11 are provided to selectively connect the Bitline pairs to the sense amplifier via a control MUX. Another pair of switches N23 and N24 is provided to selectively connect the sense amplifier with a pair of datalines DQ and bDQ. The direct sensing block includes two further pull down NMOS devices N17 and N18. When the complementary signals are developed on the Bitline pair and are being transferred to the sense amplifier, the signals are first amplified by a cross-coupled sense amplifier which is formed by a p-latch 103, and an n-latch 102. When the read signal is triggered, the direct sensing devices further enhance and develop the signal. FIG. 1 shows an exemplary 1/2 Vdd sensing scheme. After sensing, the pair of bit-lines are restored back to 1/2 Vdd level via a precharge and equalization circuit 101 formed by three nMOS devices, N12, N13 and N14. The write operation is done by directly connecting datalines to the bitline pairs without using the direct sensing devices. At the same time, the cross-coupled sensing circuit can be activated to help boost the incoming signals.
Unlike the present invention, the prior art uses a complementary signal development. In other words, a pair of true and complement signals is used for each write or read operation. The prior art also uses 1/2 Vdd sensing, and therefore requires precharge and equalization circuit. Unlike the prior art, the present invention does not use complementary signal development, uses a Vdd precharging sensing scheme applied to the sense node, and conducts dynamic discharge during sensing.
FIG. 2 shows another prior art approach similar to that of FIG. 1, except that the incoming WDQ and bWDQ and out-going RDQ and bRDQ dataline pairs are separated. In this case, although the number of datalines is doubled, it is possible to perform different operations simultaneously on different banks of the DRAM. The direct sensing part 204 is exactly the same as 104 shown in FIG. 1 with no fundamental difference therebetween.
FIG. 3 illustrates a prior invention disclosure which is not necessarily prior art (disclosure #YOR920000469US1) which is a direct sensing alternative which uses a current sensing scheme. The initial state of the sense amplifier is that the BL is precharged to Vpre through devices N2 and P1, with Vpre being a voltage close to Vref, which is applied to the gate of transistor N3. The relation of Vpre and Vref is such to place the device N3 in the sub-threshold region. The sense line SL is precharged to VDD through device P2 and the node NDO is precharged to ground through the device N6.
During the sensing of a xe2x80x980xe2x80x99 data type, the BL develops a signal and results in a gate-source voltage below the threshold of the N3 transistor. Because the nFET is biased in the subthreshold region, the current flowing therethrough is exponentially related to the gate-source voltage. Thus, very small signals can be detected. As current flows through N3, the capacitance of the sense line is discharged until it turns on the pFET P3. This pulls up the node NDO and registers that a 0 is sensed from the BL. The transfer gate formed by devices N9 and P4, as well as devices N4 and N5, and inv1 are activated to feed the signal back to the BL to restore the signal to the cell after the sensing operation.
The reading of a xe2x80x981xe2x80x99 data type does not result in a change of the SL and NDO node potentials since the device N3 remains off. However, the full signal is still restored to the BL via the N9/P4 transfer gate, N4, N5 and inv1.
The present invention differs from the current sensing approach of FIG. 3 in that it relies on the pFET threshold voltage (devices P1/P2 of FIG. 6) to detect the signal level. The resulting design produces a full swing output as shown by the waveforms in FIG. 7 with a significant reduction in the number of devices in the primary sense amplifier. By comparison, YOR9-2000-0469 is not as simple, has more transistors, and requires two more voltages Vpre and Vref.
FIG. 4 illustrates a prior invention disclosure which is not necessarily prior art (disclosure #BUR820000488) which utilizes the direct sense for the write operation (devices N1/N2) and the read operation (devices N5/N6), which is equivalent to the 104 and 105 circuit portions in the prior art of FIG. 1. Unlike FIG. 1, however, the full signal development and writeback devices (the cross-coupled pair) are moved to the secondary sensing circuitry to reduce the sense amplifier size. Further, it performs the conversion of a bitline pair to a single output signal line MDQ by utilizing devices N5 and N6 controlled by signals RD0 and RD1. Finally, it controls the BL and /BL precharge devices (P1 and P2 controlled by signals EQ0 and EQ1) independently, and thus provides for BL-BL noise shielding during the sensing operation.
Although the present invention contains one more device per BL than the prior art of FIG. 4, an advantage over the design of the present invention is that no critical timing of the sense amplifier control signal is requiredxe2x80x94once the circuit is precharged, the BL either swings enough to trip the circuit, or it does not. Finally, unlike the prior art of FIG. 4, in the present invention the polarity of the BL and MDQ nodes is the same. Thus, the devices N7/N8 of FIG. 6 can be used to write the data back into the BL at the primary sense amplifier.
FIG. 5 illustrates another prior art approach which uses direct sensing to reduce the number of devices of the sense amplifier. As shown in FIG. 5, the write and read control signals are shared. When the write control signal WE=1, a write operation is issued, otherwise a read operation is defined, which eliminates a pair of switches and a control signal wire.
During a read operation when WE=0, two nMOS devices N305 and N306 become the pair of pull-down NMOS devices, which are similar to N117 and N118 respectively of FIG. 2. At this moment, two write devices N303 and N304 are shut off. The concern here is that the line WE not only serves as the signal line, but also serves as the low-impendence ground power line. The wiring of the line WE has to be sufficiently wide to ensure high current sinking for high-speed switching.
During a write operation when WE=1, data are directly fed from DQ and bDQ to the corresponding bitline pairs. In all three examples mentioned herein, a cross-coupled sense amplifier component is used to enhance the read signal on the bit line and to provide for a means to write-back the data to the memory cell after the read operation.
Accordingly, it is a primary object of the present invention to provide a DRAM direct sensing scheme.
A further object of the subject invention is the provision of a DRAM direct sensing scheme which does not use the development of true and complementary signals, uses a Vdd precharging sensing scheme applied to a sense node, and conducts dynamic discharge during sensing.
In accordance with the teachings herein, the present invention provides a DRAM direct sensing scheme which maintains the same polarity (even number of signal inversions) between the bitline BL signal and the dataline DQ signal, such that the primary sense amplifier can be employed to write-back data into the storage capacitor of the memory cell.